The present invention relates to a signal processing circuit, and particularly to a signal processing circuit including, e.g., a common arithmetic operation element used commonly by a plurality of programmable sequencers.
Conventionally, a programmable controller capable of executing a plurality of sequence programs in parallel has been known. For example, the programmable controller of Patent Document 1 (Japanese Unexamined Patent Publication No. 2009-116445) includes program execution circuits (3a1 to 3an) which are a plurality of dedicated LSIs as hardware capable of executing a predetermined first instruction included in sequence programs, and a CPU (1) for executing a second instruction which is included in the plurality of independent sequence programs being executed in parallel and which cannot be executed in the program execution circuits. The programmable controller further includes a first transfer means for transferring information items on the at least one second instruction to the CPU (1) in chronological order, and a second transfer means for transferring the information items on the second instruction executed by the CPU (1) to the program execution circuits. The programmable controller performs priority control in which, when a plurality of requests to write to a FIFO are simultaneously given from the plurality of program execution circuits, the request from the program execution circuit having a higher priority is prioritized.